datasheet lvhstl to cmos clock divider ics558-02 idt? / ics? lvhstl to cmos clock divider 1 ics558-02 rev d 020504 description the ics558-02 accepts a high-speed lvhstl input and provides four cmos low skew outputs from a selectable internal divider (divide by 3, divide by 4). the four outputs are split into two banks of two outputs. each bank has a separate output enable to tri-state the output buffers. the ics558-02 is a member of the ics clock blocks tm family of clock generation, synchronization, and distribution devices. features ? 16-pin tssop package ? lvhstl inputs ? accepts up to 250 mhz input frequency ? four low skew (<250 ps) outputs ? selectable internal divider of 3 or 4 ? operating voltage of 3.3 v block diagram oe1 clk1 clk2 clk3 clk4 hclk output divide /3 or /4 hclk sel gnd vdd oe0 4 3
ics558-02 lvhstl to cmos clock divi der lvhstl clock divider idt? / ics? lvhstl to cmos clock divider 2 ics558-02 rev d 020504 pin assignment tri-state table output divide selection pin descriptions 12 1 11 2 10 3 9 sel 4 vdd 5 vdd 6 vdd 7 hclk 8 hclk clk1 clk2 clk3 gnd clk4 oe1 gnd gnd 16 15 14 13 oe0 vdd 16 pin 173 mil (0.65mm) tssop oe1 oe0 clk 1, clk 2 clk 3, clk 4 0 0 tri-state tri-state 0 1 clock on tri-state 10 tri-state clock on 1 1 clock on clock on sel output divide 0/3 1/4 pin number pin name pin type pin description 1 sel input select pin for output divider. see table above. internal pull-up to vdd. 2 vdd power connect to +3.3 v. 3 vdd power connect to +3.3 v. 4 hclk input differential lvhs tl input (true input). 5 hclk input differential lvhstl input (complimentary input). 6 gnd power connect to ground. 7 gnd power connect to ground. 8 oe0 input output enable for clk1 and clk2. see table above. internal pull-up to vdd. 9 oe1 input output enable for clk3 and clk4. see table above. internal pull-up to vdd. 10 gnd power connect to ground. 11 clk4 output low skew clock output. 12 clk3 output low skew clock output. 13 clk2 output low skew clock output. 14 clk1 output low skew clock output. 15 vdd power connect to +3.3 v. 16 vdd power connect to +3.3 v.
ics558-02 lvhstl to cmos clock divi der lvhstl clock divider idt? / ics? lvhstl to cmos clock divider 3 ics558-02 rev d 020504 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics558-02. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd=3.3 v 5% , ambient temperature 0 to +70 c, unless stated otherwise stated. item rating supply voltage 4.6 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature 0 to +70 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 +70 c power supply voltage (measured in respect to gnd) +3.15 +3.3 +3.5 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.135 3.3 3.465 v operating supply current idd no load, 100 mhz 60 ma input high voltage v ih oe pins vdd-0.5 vdd v input low voltage v il oe pins 0.5 v input high voltage v ih hclk vx + 0.1 1.2 v input low voltage v il hclk -0.3 vx - 0.1 v peak to peak input voltage hclk 0.3 1.0 v hclk input leakage current i il -20 20 a input common mode voltage vx input common mode 0.68 0.90 v output high voltage v oh i oh = -14.5 ma 2.4 v output low voltage v ol i ol = 9.4 ma 0.4 v nominal output impedance z o 20 w internal pull-up resistor r pu 250 k ? input capacitance c in 7pf
ics558-02 lvhstl to cmos clock divi der lvhstl clock divider idt? / ics? lvhstl to cmos clock divider 4 ics558-02 rev d 020504 ac electrical characteristics vdd = 3.3 v 5% , ambient temperature 0 to +70 c, unless stated otherwise stated. thermal characteristics (16-pin tssop) parameter symbol conditions min. typ. max. units input frequency 0 250 mhz output rise time t or 0.4 to 2.4 v, c l =30 pf 0.5 1.1 2.0 ns output fall time t of 2.4 to 0.4 v, c l =30 pf 0.5 1.0 2.0 ns skew (between any two output clocks) 30 pf load 0 250 ps propagation delay 9 12 ns output clock duty cycle at vdd/2, c l =30 pf 45 50 55 % parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w
ics558-02 lvhstl to cmos clock divi der lvhstl clock divider idt? / ics? lvhstl to cmos clock divider 5 ics558-02 rev d 020504 package outline and package dimensions (16-pin tssop, 4.40 mm body, 0.65 mm pitch) package dimensions are kept current with jedec publication no. 95, mo-153 ordering information while the information presented herein has been checked for both a ccuracy and reliability, integrat ed circuit systems (ics) ass umes no responsibility for either its use or for the infringement of an y patents or other rights of third parties, which would result f rom its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves th e right to change any circuitr y or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. part / order number marking (both) shipping packaging package temperature 558g-02 ics558g-02 tubes 16-pin tssop 0 to 70 c 558G-02T ics558g-02 tape and reel 16-pin tssop 0 to 70 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l millimeters inches symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 a0 8 0 8 aaa -- 0.10 -- 0.004
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